1. Field of the Invention
This disclosure relates to fabrication methods of a semiconductor device and, more particularly, to fabrication methods of a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby.
2. Description of Related Art
As semiconductor devices become more highly integrated, a trench isolation technique has been widely used in order to separate the adjacent discrete devices. The trench isolation technique includes etching a predetermined region of a semiconductor substrate to form a trench region and forming an isolation layer that fills the trench region.
FIGS. 1 to 3 are cross sectional views for illustrating a conventional trench isolation technique.
Referring to FIG. 1, a pad oxide layer 3 and a pad nitride layer 5 are sequentially formed on a semiconductor substrate 1. The semiconductor substrate 1 has a low voltage MOS transistor region A and a high voltage MOS transistor region B. The low voltage MOS transistor region A may be a portion of a cell array region in a flash memory device or a portion of a peripheral circuit region in the flash memory device. The pad nitride layer 5 and the pad oxide layer 3 are patterned to expose predetermined regions of the semiconductor substrate 1. The exposed semiconductor substrate 1 is etched using the patterned pad nitride layer 5 as an etching mask. As a result, first trench regions 9a are formed in the low voltage MOS transistor region A, and second trench regions 9b are formed in the high voltage MOS transistor region B. The first trench regions 9a define first active regions 7a in the low voltage MOS transistor region A, and the second trench regions 9b define second active regions 7b in the high voltage MOS transistor region B. First and second isolation layers 11a and 11b are formed in the first and second trench regions A and B, respectively. The first and second isolation layers 11a and 11b are formed of a silicon oxide layer.
Referring to FIG. 2, the patterned pad nitride layer 5 and the patterned pad oxide layer 3 shown in FIG. 1 are removed using a wet etching technique, thereby exposing the first and second active regions 7a and 7b. As a result, first recessed regions 13, i.e., dent regions are formed at edges of the first and second isolation layers 11a and 11b. The substrate having the first recessed regions 13 is then thermally oxidized to form a first gate oxide layer 15 on the exposed active regions 7a and 7b. The first gate oxide layer 15 on the second active regions 7b exists even though subsequent processes are performed, and the first gate oxide layer 15 acts as a gate insulating layer of a high voltage MOS transistor. The thicker the first gate oxide layer 15 is, the thinner the first gate oxide layer on the edge corners of the second active regions 7b is, relatively. This phenomenon is called “thinning effect”.
Referring to FIG. 3, the first gate oxide layer 15 in the low voltage MOS transistor region A is selectively removed to expose the first active regions 7a. As a result, second recessed regions 13a, which are deeper than the first recessed regions 13, are formed at the edges of the fist isolation layers 11a. The substrate having the second recessed regions 13a is then thermally oxidized to form a second gate oxide layer 17, which is thinner than the first gate oxide layer 15, on the first active regions 7a. The first gate oxide layer 15 on the second active regions 7b is hardly grown during formation of the second gate oxide layer 17. Accordingly, the first gate oxide layer 15 has almost the same thickness as the initial thickness thereof. Nevertheless, the first recessed regions 13 still exist at the edges of the second isolation layers 11b, and the second recessed regions 13a, which are deeper than the first recessed regions 13, also exist at the edges of the first isolation layers 11a. 
A gate conductive layer 19 is formed on an entire surface of the semiconductor substrate including the second gate oxide layer 17. As a result, the first gate oxide layer 15 acts as a gate insulating layer of a high voltage MOS transistor, and the second gate oxide layer 17 acts as a gate insulating layer of a low voltage MOS transistor. The gate conductive layer 19 is then patterned to form first gate electrodes (not shown) that cross over the first active regions 7a and second gate electrodes (not shown) that cross over the second active regions 7b. 
According to the foregoing conventional art, the first recessed regions are formed at the edges of the second isolation layers in the high voltage MOS transistor region, and the second recessed regions, which are deeper than the first recessed regions, are formed at the edges of the first isolation layers in the low voltage MOS transistor region. Accordingly, subthreshold characteristics of the high voltage MOS transistor as well as the low voltage MOS transistor are remarkably degraded. In particular, a breakdown voltage of the gate oxide layer of the high voltage MOS transistor is remarkably lowered, since the first gate oxide layer 15 covering the edge corners of the second active regions 7b is relatively thinner than that on the central regions of the second active regions 7b. As a result, reliability of the high voltage MOS transistor is degraded.
To address this problem, a self-aligned trench isolation technique has been proposed in order to prevent the recessed regions from being formed. The self-aligned trench isolation technique is taught in U.S. Pat. No. 6,222,225 to Nakamura et al., entitled “Semiconductor device and manufacturing method thereof”.
FIGS. 4 to 7 are cross sectional views for illustrating the self-aligned trench isolation technique described in the U.S. Pat. No. 6,222,225, and FIG. 8 is an overhead view for showing a problem that may occur in the self-aligned trench isolation technique according to the U.S. Pat. No. 6,222,225.
Referring to FIG. 4, a gate insulation layer, a first floating gate layer and a silicon nitride layer are sequentially formed on a semiconductor substrate 21. The silicon nitride layer, the first floating gate layer and the gate insulation layer are successively patterned to expose predetermined regions of the semiconductor substrate 21. The exposed semiconductor substrate 21 is selectively etched to form trench regions 23 that define active regions 22. As a result, a tunnel oxide layer 25, a first floating gate pattern 26a and a polishing stop layer pattern 41, which are sequentially stacked, are formed on each of the active regions 22. An insulation layer 24 is formed in the trench regions 23 and on the polishing stop layer patterns 41.
Referring to FIG. 5, the insulation layer 24 is planarized until the polishing stop layer patterns 41 (not indicated in FIG. 5) are exposed, thereby forming isolation layers 24a in the trench regions 23. The exposed polishing stop layer patterns 41 are selectively removed to expose the first floating gate patterns 26a. As a result, the isolation layers 24a are relatively protruded from the top surfaces of the first floating gate patterns 26a. In addition, the protrusions of the isolation layers 24a have negative sloped sidewalls as shown in FIG. 5. In other words, the sidewalls of the protrusions exhibit inverted tapered shape. The negative sloped sidewalls may lead to difficulties in subsequent processes.
Referring to FIG. 6, the isolation layers 24a are isotropically etched to convert their sidewall profiles into a positive sloped shape. As a result, recessed regions R are formed at edges of the isolation layers 24a as shown in FIG. 6. Here, the isotropic etching is appropriately performed so that the recessed regions R do not expose the tunnel oxide layer 25. Thus, the recessed regions R do not affect the subthreshold characteristic of a MOS transistor.
Referring to FIG. 7, a second floating gate layer is formed on an entire surface of the substrate having the recessed regions R. The second floating gate layer is patterned to form second floating gate patterns 26b that cover the active regions 22. The first and second floating gate patterns 26a and 26b, which are sequentially stacked on each of the active regions 22, constitute a floating gate pattern 26. An inter-gate dielectric layer 27 and a control gate electrode layer are sequentially formed on an entire surface of the substrate having the floating gate patterns 26.
Subsequently, the control gate electrode layer, the inter-gate dielectric layer 27 and the floating gate patterns 26 are successively patterned to form control gate electrodes 28 crossing over the active regions 22 as well as floating gates 26 interposed between the control gates 28 and the active regions 22. During formation of the control gate electrodes 28 and the floating gates 26, stringers S may be formed at edges of the isolation layers 24a between the adjacent control gate electrodes 28 as shown in FIG. 8. The stringers S are formed in the recessed regions R shown in FIG. 6. That is, the stringers correspond to residues of the second floating gate patterns 26b. 
As described above, the isolation layers fabricated according to the conventional trench isolation technique and the conventional self-aligned trench isolation technique may exhibit various problems.
Embodiments of the invention address these and other limitations in the prior art.